Forum

Theme 6: Image Sensor

An image sensor that converts an optical image into an electronic signal is one of the most

essential elements of mobile phones, cameras, CCTV, and bio sensors. The most currently 

used  types  are digital charge-coupled device (CCD)  and complementary metal–oxide–

semiconductor (CMOS) active pixel sensors. Recently, miniaturization trend of IT equipment, reduced price, and advancement of technology requires more  innovative image sensor technology.

SAMSUNG invites your innovative ideas in this theme.

The subjects of special interest in this theme of 2012 are as below, but not limited to these:

1. High Resolution Computational Imaging based on Camera 2.0

2. Development of High Performance in Sub-1um Pixel and Simulation Environment

3. Energy Efficient Column Parallel Two Step ADCs for High Speed Imaging

4. Resolution Enhancement of Image from Low Resolution Image

5. Smart Image Sensor

6. Si Photonic Biosensor for Healthcare

Subject 1: High Resolution Computational Imaging based on Camera 2.0

Introduction

Computational imaging is the combination of novel optics and computations strategies to produce images that cannot be captured with traditional camera imaging. It can provide ultra slim thickness of camera module, depth information based gesture recognition, refocusing, and so on. 

Although there has been much interest in computational imaging, progress has been hampered by the lack of a portable, programmable camera with sufficient image quality and computing power. To address this problem, Camera 2.0 has been proposed as an open architecture and API for such cameras. The architecture permits control and synchronization of the sensor and image processing pipeline at the microsecond time scale, as well as the ability to incorporate and synchronize external hardware like lenses and flashes.

Computational cameras have been used for industrial application. But they have not been used for mobile application, especially mobile phone camera. This is because that they cannot high resolution image output. For example, refocusing camera generates 2M image from 16Mp sensor. In other words, we have to use 64Mp sensor to get 8M resultant image. 

Scope

We are interested in high resolution computational imaging with the following properties

- Methods to refocus and estimate depth from computational (plenoptic) camera and  Camera 2.0 platform

- Methods to get high resolution output image and/or depth from plenoptic camera.

- Methods to operate computational camera in low power-consumptionPage 2

Research questions

We are interested in the following research questions. Any research participation or open discussion will be welcomed.

- When implementing plenoptic camera as very thin camera module, are there any problem expected?

- There may be trade-off between output resolution and refocusing performance. How can we increase output resolution while keeping refocusing performance?

- Can super-resolution techniques increase output resolution? Are there any artifact or resource limitation from super-resolution?

Expected Deliverables

Result of the research idea in the form of technical documentation and C/C++ algorithm codes

Subject 2: Development of High Performance in Sub-1um Pixel and Simulation Environment

Introduction

Pixel pitch of image sensors gets smaller and smaller to make higher resolution on same sensor size. Then incident optical power per pixel decreases, and it becomes difficult to obtain high quantum efficiency and low crosstalk. Therefore it is very essential to develop a novel optical structure which helps to overcome the limitation of conventional pixel performance.

The goal of this project is to explore new optical structure of pixels in CMOS image sensor to maximize pixel performance such as quantum efficiency, sensitivity, and crosstalk. This includes any novel structure or material which enhances light gathering power, transmission efficiency, absorption power.

Scope

Challenges that significantly advance the state-of-the-art in pixel technologies include:

- New microlens structure to reduce diffraction and enhance light gathering efficiency in the submicron pixel sensor

- New methods to enhance light absorption power in the submicron pixel sensor

- New methods include new material as well as new optical structure

- Novel concepts (e.g. surface plasmon, multiple electron generation, etc.) are also welcomed.

- New color filter material and structure to improve SNR with good color accuracy

- Theoretical study and any possible experiment are also recommended.

- Simulation method to increase speed and accuracy

Research questions

We are interested in the following research questions. Any research participation or open discussion will be welcomed.

- How can we control the diffraction of the lens between pixels to reduce the crosstalk in the submicron pixel sensor?

- How can the light gathering power of microlens be improved in the sub-micron pixels?

- How to remove loss of power in sub-micron pixels?

- Additional Structures to enhance the absorption power in the submicron pixel sensor.

- What is the ideal color filter spectrum to improve SNR?

- What is the best simulation method to improve speed and accuracy? 

Expected Deliverables

- Report on theoretical study

- Report on experimental analysis.

- Raw data and tool for simulation/analysis.

Subject 3: Energy Efficient Column Parallel Two Step ADCs for High Speed Imaging

Introduction

The demands for high resolution, high frame-rate, and low noise CMOS image sensors continue to push the performance of high-speed analog-to-digital converters(ADCs). The goal of this project is to realize energyefficient column-parallel two-step ADCs for use in high-speed CMOS image sensors. Based on our expertise in the design of energy-efficient sensor interfaces, we plan to develop ADCs for CMOS image sensors that are both high-speed and energy-efficient. To do this, we will concentrate on the design of new column-parallel twostep ADCs.

The ever increasing frame rate and resolution of CMOS image sensor requires high speed analog-to-digital conversion. As a result, column-parallel ADC architectures have become increasingly popular, because they offer a good trade-off between frame-rate, number of columns, noise performance, and power consumption. 

Since a single-slope (SS) ADC can be implemented with a very simple column circuit consisting of a single comparator and a counter, it will typically require much less chip area than other approaches, such as cyclic, SAR, and ΔΣ. Moreover, this simple column circuit makes it relatively easy to ensure uniformity among columnsand thus minimizes the amount of column fixed-pattern noise (FPN). However, a disadvantage of a SS ADC is its relatively slow conversion speed. Each n-bit A/D conversion requires 2n clock periods, compared with only n clock cycles for SAR or cyclic ADCs. This can limit the readout speed of the imager and increase the power consumption, particularly at high resolution (>10bit) imagers.

Scope

We are interested in a two step ADC regarding the embodiment of low power & high speed CIS:

- Optimization of CIS readout architecture to overcome the two step ADC’s weakness 

- ADC type to improve the productivity as well as size, speed, and power

- Structure innovation for energy-efficient two-step ADC having ultra low noise 

Research questions

We are interested in the following research questions. Any research participation or open discussion will be welcomed.

- How can we get over all the obstacles, especially the trade-off relation between power, speed, and noise when designing a next CIS ADC?

- How can we secure the uniformity and productivity as well as IP’s performance?

- How can we get over the size competitiveness of original single slope ADC as well as power efficiency?

Expected Deliverables

- Schematic & Layout DB

- Experiment and analysis report

- Prototype devices

- Patents (if agreed)

Subject 4: Resolution Enhancement of Image from Low Resolution Image

Introduction

Single frame super-resolution technology can provide high resolution image from low resolution image without zoom lens. The single frame super-resolution can be a promising alternative to conventional superresolution approaches which require multiple frames of memory. This technology is especially important to mobile applications where limited memory and computational resources are required. However current state-of art single frame super-resolution approaches still suffer from problems of image artifacts and high 

computational complexity.

The goals of this research are to developing and refining a new single frame super-resolution technology to overcome above problems.

Scope

Challenges that significantly advance the state-of-the-art in image upscaling technologies include:

- Image upscaling based on self-similarity of an input image.

- Reducing artifacts and improve naturalness of the upscaled image

- Reducing required line memory and computational complexity of upscaling algorithm

Research questions

We have special interests in the following questions. Any research participation or open discussion will be welcomed.

- How to reduce artificial and unnatural representation of upscaled image to complex textured input image?

- How to define similarity among similar patterns? If we have similarity measure, how to use this similarity to stitch and upscale high resolution image?

- How to reduce computational redundancy in cascaded processing of self-similarity based upscaling?

Expected Deliverables

Deliverables can be architecture proto type, experiment & analysis reports, SW tools or models according to the characteristics of the research.

Subject 5: Smart Image Sensor

Introduction

A variety of innovations have been made in functional imaging technologies in the era of smart electronics. Such trend boosts interdisciplinary research and business development trend. For example, three dimensional image sensors have been developed from the combinatorial research efforts in such fields of CMOS image sensor, solid-state lighting, image signal processing, and commercialized successfully in consumer electronics market. To cope with various demands of functionalities in emerging smart electronics, we are in search of research proposal which suggests outstanding smart functional imaging technology. The proposal should be convincing in consideration of feasibility in pixel and system level realization, and consider the compatibility with CMOS fabrication procedure. Parts of, or all of the proposition may be realized in cooperation with Samsung Electronics after investigation. Original proposals are solicited in the following scopes, but not restricted to:

Scopes

- Advanced smart functional imaging technologies, especially in the field of health-care, natural  user interface, virtual reality, etc.

- Pixel, circuit, image signal processing, optics, module and any other system level architectures covering the above mentioned area.

- Unprecedented pixel, circuit, and system level core technologies, such as  three dimensional imaging, cognitive imaging, imaging in non-visible wavelength range, infrared-to-visible converting imaging, single transistor CMOS imaging, etc.

- Image  signal processing algorithm which accounts for effectiveness in smart functionalities, such as smart pattern and motion recognition, etc.

- Methodology of analysis and characterization in pixel and system level for advanced smart imaging devices.

Research questions

- Why do the new smart functionalities of proposition bear technological impact and possibly open new consumer electronics markets in regards of image sensor? 

- How can the proposition be realized with new architectures?

- How can the proposition be realized in practice? For instance, is the proposition achievable with current CMOS technologies? Would the power of electrical consumption and operational speed be acceptable?

- Why do the methodology of analysis and characterization of proposition bear academic and technological importance and effectiveness?

Expected Deliverables

Deliverables can be in various forms depending on the characteristics of the research activities, such as analysis and experimental reports, prototypical architecture, software tools and demonstrating  hardware, etc.